Design and Implementation of an Improved BIST Architecture for ROM

Authors

  • D. Prasanthi M.Tech Student (VLSI & Embedded System), Dept. of Electronics & Communication Engineering, Gandhiji Institute of Science and Technology, Bhimavaram, Andhra Pradesh, India
  • A.H.Sharief Professor, Dept. of Electronics & Communication Engineering, Gandhiji Institute of Science and Technology, Bhimavaram, Andhra Pradesh, India

DOI:

https://doi.org/10.51983/ajes-2017.6.1.1995

Keywords:

Built-in-self test; testing; design for testability, circuit under test, Concurrent BIST Unit, Error detecting unit

Abstract

Input vector monitoring online testing schemes perform testing during the normal operation of the circuit. These schemes are evaluated based on hardware overhead and concurrent test latency (CTL), also well suited for modules requiring exhaustive testing, such as Read Only Memories (ROMs). In this work we present an input vector monitoring concurrent BIST scheme specially designed for the testing of ROM modules along with an error detecting unit which can detect error of corresponding bit position. By using circuitry already existing for the memory module, the hardware overhead, power and the delay, compared to previously proposed schemes, is significantly reduced.

References

I. Voyiatzis and C. Efstathiou, "Input Vector Monitoring Concurrent BIST Architecture using SRAM cells," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 7, pp. 1625-1629, Jul. 2014.

I. Voyiatzis, T. Haniotakis, C. Efstathiou, and H. Antonopoulou, "A concurrent BIST architecture based on monitoring square windows," in Proc. 5th Int. Conf. DTIS, Mar. 2010, pp. 1-6.

K. K. Saluja, R. Sharma, and C. R. Kime, "Concurrent comparative built-in testing of digital circuits," Dept. Electr. Comput. Eng., Wisconsin, Madison, WI, USA, Tech. Rep. ECE8711, 1986.

I. Voyiatzis, A. Paschalis, D. Gizopoulos, N. Kranitis, and C. Halatsis, "A concurrent BIST architecture based on a self-testing RAM," IEEE Trans. Rel., vol. 54, no. 1, pp. 69-78, Mar. 2005.

I. Voyiatzis and C. Halatsis, "A low-cost concurrent BIST scheme for increased dependability," IEEE Trans. Dependable Secure Comput., vol. 2, no. 2, pp. 150-160, Apr. 2005.

K. K. Saluja, R. Sharma, and C. R. Kime, "A concurrent testing technique for digital circuits," IEEE Trans. Comput. Aided Design Integr. Circuits Syst., vol. 7, no. 12, pp. 1250-1260, Dec. 1988.

M. A. Kochte, C. Zoellin, and H.-J. Wunderlich, "Concurrent self-test with partially specified patterns for low test latency and overhead," in Proc. 14th Eur. Test Symp., May 2009, pp. 53-58.

E. J. McCluskey, "Built-in self-test techniques," IEEE Design Test Comput., vol. 2, no. 2, pp. 21-28, Apr. 1985.

R. Sharma and K. K. Saluja, "Theory, analysis, and implementation of an on-line BIST technique," VLSI Design, vol. 1, no. 1, pp. 9-22, 1993.

I. Voyiatzis, "Online testing of ROMs with input vector monitoring," Median Workshop, 2015.

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Published

05-03-2017

How to Cite

Prasanthi, D., & A.H.Sharief. (2017). Design and Implementation of an Improved BIST Architecture for ROM. Asian Journal of Electrical Sciences, 6(1), 7–14. https://doi.org/10.51983/ajes-2017.6.1.1995

Issue

Vol. 6 No. 1 (2017): January-June 2017

Section

Articles

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